An MPEG decoder system is usually implemented as an off the shelf integrated circuit that is fused onto a mother board. Other end product functionalities are usually implemented as other board-level products. Because the decoding and other functionalities are usually manufactured separately, it is important to debug, test, and verify the video control functionality. Testing the video functionality can involve application of particular video control functions, e.g., reverse, fast forward, etc. However, given the number of frames per second, it is difficult for the human eye to determine the ordering of pictures displayed during testing.
Additionally, the testing can include the display of particular line patterns. However, a single line pattern may not appear large enough on a display for visual inspection. By repeating the line pattern for a number of lines, the test pattern can be observed as a set of vertical bars.
The repeated line pattern can be displayed by generation of a frame comprising the repeated lines. However, generation of the repeated lines disadvantageously consumes the bandwidth of the decoder system.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with embodiments presented in the remainder of the present application with references to the drawings.